Research line coordinated by Gianluca Susi.
Computational neuroscience is an interdisciplinary field which employs mathematical models and theoretical analysis to understand the principles that govern the physiology, structure and development of the nervous system, and related cognitive abilities. Specifically, in the laboratory we carry out brain network simulations based on real data, aimed at reproducing network connectivity in health and disease.
G. Susi, I. Suárez Méndez, D. López Sanz, M. E. López García, E. Paracone, E. Pereda, F. Maestu. Hippocampal volume and functional connectivity transitions during the early stage of Alzheimer’s disease: a Spiking Neural Network-based study. 28th Annual Computational Neuroscience Meeting: CNS*2019. – BMC Neuroscience 2019, 20 (Suppl 1).
G. Susi, J. de Frutos Lucas, G. Niso, S.M. Ye Chen, L. Ant´on Toro, B.N. Chino Vilca, and F. Maestu. Healthy and pathological neurocognitive aging: Spectral and functional connectivity analyses using magnetoencephalography. In OXFORD RESEARCH ENCYCLOPEDIA OF PSYCHOLOGY AND AGING. Oxford University press, 2019.
G, Susi L. Antón Toro, L. Canuet, M. E. López, F. Maestú, C.R. Mirasso, E. Pereda. A Neuro-Inspired System for Online Learning and Recognition of Parallel Spike Trains, Based on Spike Latency, and Heterosynaptic STDP. Front Neurosci. 2018; 12:780.
G. Susi, S. Acciarito, T. Pascual, A. Cristini, and F. Maestu. Towards neuro-inspired electronic oscillators based on the dynamical relaying mechanism. International Journal on Advanced Science, Engineering and Information Technology, 9(2), 2019.
G. Susi, F. Bartolacci, and Massarelli M. A computational approach for the understanding of stochastic resonance phenomena in the human auditory system. International Journal on Advanced Science, Engineering and Information Technology, 9(4), 2019.
S. Acciarito, G.C. Cardarilli, A. Cristini, L. Di Nunzio, R. Fazzolari, G.M.Khanal, M. Re, and G. Susi. Hardware design of LIF with latency neuron model with memristive STDP synapses. Integration, the VLSI Journal, 59:81-89, 2017.